Generally, IC devices include ESD protection circuits to divert and discharge high electrical currents caused by ESD events, which may occur during normal use of the devices, for example, when input/output terminals of an IC device are connected to other devices or circuits. Without ESD protection circuits, the high electrical currents may cause malfunction or physical damage in an IC device. Advanced IC devices utilizing FinFET technology also need and utilize ESD protection circuitry; however, traditional ESD circuits require larger silicon area and additional process steps for implementation, are limited to a fixed ESD trigger voltage (Vt1), and may be ineffective in providing sufficient protection against an ESD event. In one example, the trigger-voltage (Vt1) in an ESD circuitry may be same as the junction breakdown voltage (e.g., N-P, P-N) in an ESD circuit. As a result, the ESD circuit may be unable to effectively protect the other devices/elements from the ESD event. FIG. 1 illustrates another example solution, where an “ESD implant” 101 may be utilized to reduce the Vt1 at the collector side of the ESD device; however, this solution would require an additional fabrication mask, adding to the fabrication process.
Therefore, a need exists for methodology enabling formation of an efficient and effective ESD protection circuit for FinFET devices and the resulting devices.